PCI Bus, Bus Master, Bus Comparisons And Bus Speeds

PCI Bus

The PCI local bus (Peripheral Component Interconnect bus) is now the standard local I/O bus, not only with Pentium CPUs but also with RISC CPUs. Standard PCI has a 32-bit data path and runs at 33 MHz when the systemboard runs at 66 MHz.

However, the PCI specifications can also use a 64-bit data path and can run at a speed of 66 MHz when the system bus runs at 133 MHz. Also, an addendum to the PCI specifications, called PCI-X, enables the PCI to run at 133 MHz.

One advantage of the PCI local bus is that devices connected to it can run at one speed while the CPU runs at a different speed. Devices connected to the VESA bus must run at the same clock speed as the CPU, which forces the CPU to endure frequent wait states. The PCI bus expansion slots are shorter than ISA slots as shown in the figure below, and set a little farther away from the edge of the systemboard.

Bus Master

The PCI bus also supports bus mastering. A bus master is an intelligent device (i.e., it has a microprocessor installed that manages the device) that, when attached to the PCI bus, can gain access to memory and other devices on the bus without interrupting the action of the CPU. The CPU and the bus mastering devices can run concurrently and independently of each other.

Throughput Performance

Because of the effective design of the PCI bus, the throughput performance or the data transfer rate per second is 132 MB. Throughput performance or data throughput is a measure of the actual data transmitted by the bus, not including error-checking bits or redundant data.

Bus Comparisons And Bus Speeds

The tables below compare the buses discussed in this section. Most often when comparing buses users focus on the width of the data path and the overall bus speed. However, you also should consider the type of expansion slot the bus allows. The number of fingers on the edge connector of the expansion card and the length of the edge connector are determined by the bus that controls that expansion slot. Various bus connections are shown in the figure below.

Wait States

A wait state isn’t a systemboard component, but it is an idea that you need to understand in the overall performance of a computer system. A wait state occurs when the CPU must wait for some other component to catch up, for example when slower dynamic RAM reads or writes data. To allow time for the slow operation, the CPU is told to maintain a wait state by CMOS setup information.

If normally the CPU can do something in two clock beats, it is told to take an extra clock beat for a total of three clock beats. It works for two beats and then waits one beat, which makes for a 50-percent slowdown in speed.